1. Field of the Invention
The present invention generally relates to memory testing, and more particularly to masking the results of post-replacement testing of memory elements known to be defective.
2. Description of the Related Art
Memory chips are fabricated using state-of-the-art technologies with minimum feature-sizes implemented on the memory chips wherever possible. Memory chips are designed to allow for the storage of a large amount of information on one chip (currently 512 Mbits or more for a DRAM (Dynamic Random Access Memory) chip). One of the major determinants of the cost of producing memory chips is wafer yield, which is defined as the ratio of non-defective chips over the total chips fabricated on a given wafer. In general, the higher the integration density of a memory chip, the higher the probability that one or more memory cells of the memory chip will be defective. Thus, the higher the integration density of the chips fabricated on a given wafer, the lower the wafer yield. Accordingly, it is necessary to correct defects in order to enhance wafer yield, especially with the advent of high-density memory chips.
One effective method of correcting memory cell defects in a memory device is to provide a redundant memory cell array in addition to the normal memory cell array of the memory device. The redundant memory cell array comprises one or more redundant blocks of memory cells used to replace one or more normal blocks of memory cells of the normal memory cell array which contain defective memory cells found during testing. When a normal block of memory cells contains one or more defective memory cells, the entire block is considered defective and needs to be replaced by a non-defective redundant block.
Typically, the redundant memory cell array has one or more programmable redundancy determining units attached thereto, one for each redundant block. During testing of the memory chip, if a normal block of the normal memory cell array is found defective, the redundancy determining unit is programmed to select a non-defective redundant block if the address of the defective normal block is applied to the memory device.
The redundancy determining unit is typically programmed by blowing one or more fusible links, i.e., an address fuse, for each address bit input of the memory device. The address fuses may be conventional fuses, requiring an external device, such as a laser, for blowing. Alternatively, the address fuses may be electrically programmable fuses and the memory device may include an internal circuit for blowing the fuses. Regardless, the address fuses of the programmable redundancy determining unit are selectively blown depending on the address of the defective normal block which the associated redundant block is supposed to replace. For example, the address fuses may be selectively blown externally (e.g., by a laser), or internally, for example, utilizing an on-chip voltage or current source and a plurality of selection-circuits to select unique fuses from existing sets of fuses based on certain input-criteria (e.g., a set of address-bits, enable bits, etc.).
Conventionally, after the replacement is enabled (e.g., post-fuse), if a memory access to the defective normal block is initiated (i.e., a redundancy hit), the programmed redundancy determining unit associated with the replacing redundant block selects the replacing redundant block and stops the selection of the defective normal block.
To properly test for defective memory cells, testing of the interdependency between adjacent cells is of particular importance. A memory cell might be functional in very simple tests, but might fail if adjacent cells behave in a certain way. As an example, a row of memory cells may pass a test when one adjacent row of memory cells contains a first test pattern but may fail the same test when another adjacent row of memory cells contains a second test pattern. Accordingly, the interdependency between adjacent cells has to be tested in order to ensure that the memory device will not fail in user applications.
Conventionally, testing of the interdependency between adjacent cells must be performed prior to replacing defective memory cells with redundant memory cells. This is because prior to any replacement, the normal blocks and the redundant blocks can be accessed in their own address spaces. As a result, testing of interdependency between adjacent cells can be easily carried out by accessing adjacent blocks. After replacement, however, the replacing redundant block is mirrored (or mapped) from the redundant address space into the normal address space at the location of the replaced normal block. As a result, testing of the interdependency between adjacent rows involving a replaced normal row cannot be properly performed.
After front-end testing and replacement of defective fuses, an accelerated aging (burn-in) test is typically performed. After the burn-in tests, the memory devices are typically packaged and a back-end-test is performed to check whether the memory devices still conform to a set of specifications. Because performance of the chip may deteriorate during the burn-in tests, front-end tests are typically run to specifications that are somewhat more stringent than the back-end tests. Because conventional techniques do not allow for testing interdependencies between adjacent memory-cells during back-end testing, these tests are moved into the front-end test. Accordingly, these tests are performed against the more stringent front-end specifications, which results in a higher amount of failing chips and unnecessary yield-losses.
Accordingly, there is a need for an apparatus and method for performing post-replacement (back end) testing of memory devices which overcomes shortcomings existing in the prior art.